1. Technical Field
This invention relates to an apparatus for generating an internal clock signal for a synchronous semiconductor memory device (e.g., Synchronous DRAM), and, more particularly, an apparatus for generating an internal clock signal synchronized with an externally applied system clock signal.
2. Discussion of the Related Art
Generally, a synchronous semiconductor memory device generates an internal clock signal in response to a system clock. An internal clock signal is a reference signal for controlling all the operations to write/read data in/from a selected memory device. To generate the internal clock signal, the synchronous semiconductor memory device employs a clock buffer that responds to an externally applied system clock signal. By using such a clock buffer, the system clock signal do no have the same phase difference as the internal clock signal. Therefore, with the system clock signal applied to the memory chip, the internal operation of the chip is delayed by such phase difference.
Methods for eliminating the phase difference include clock recovery by use of a phase locked loop or a delay locked loop. However, a certain amount of time is needed for generating the internal clock using a phase locked loop or a delay locked loop, thereby increasing the total standby current even when the device is not in operation (i.e., the device is in stand-by mode).
Another approach to reducing a clock skew and generating an internal clock signal completely synchronized with an external system clock signal is using a voltage-controlled delay line. A voltage-controlled delay line can be a synchronous delay line (SDL) circuit, or a synchronous mirror delay (SMD) circuit.
FIG. 1 is a schematic block diagram of a conventional SMD circuit, and FIG. 2 is a detailed block diagram of a delay group 50 of the SMD circuit of FIG. 1.
The SMD circuit shown in FIG. 1 includes an input buffer IBUF, a delay compensation circuit DCC, a forward delay array FDA 10, a mirror control circuit MCC 20, a backward delay array BDA 30, and an output buffer INTBUF. A delay group 50 includes the FDA 10, the mirror control circuit MCC 20, and the backward delay array BDA 30. FIG. 2 shows a detailed block diagram of the delay group 50 of FIG. 1, including a plurality of serially-connected delay units FD 1 to FDn of the forward delay array FDA 10, a plurality of phase detectors PD1 to PDn of the mirror control circuit MCC 20, a plurality of serially-connected delay units BD1 to BDn of the backward delay array BDA 30, and dummy loads DL1 to DLn 40.
Referring now to FIGS. 1 and 2, the input buffer IBUF receives an external clock signal XCLK and generates a reference clock signal PCLK.
The delay compensation circuit DCC delays the reference clock signal PCLK from the input buffer IBUF by a predetermined time ‘d1’.
The forward delay array 10 includes a plurality of serially-connected delay units FD1 to FDn and generates a plurality of delayed clock signals FOUTi, where i=1−n. The delay units FD1 to FDn of the forward delay array 10 are under the control of the mirror control circuit 20. Each of the delay units FD1 to FDn is set to have a same delay time ‘TCC−(d1+d2+d3)’.
The mirror control circuit 20 includes a plurality of phase detectors PD1 to PDn, each of which receives a reference clock signal from the input buffer and the delayed clock signal FOUTi from the corresponding delay unit FDi in the forward delay array 10. Each phase detector PDi detects whether the reference clock signal PCLK has the same phase as the delayed clock signal FOUTi. Namely, the mirror control circuit 20 detects a delayed clock signal FOUTi having a phase difference of one cycle ‘TCC’ with respect to the reference clock signal from the input buffer IBUF. Here, the delayed clock signal FOUTi is delayed by the delay time ‘d3’ of the mirror control circuit 20 into a delayed clock signal MOUTi.
The backward delay array 30 includes a plurality of serially-connected delay units BD1 to BDn. The respective delay units BDi are constructed to have the same delay time ‘TCC−(d1+d2+d3)’ as the respective delay units of the forward delay array 10.
The output buffer INTBUF delays a clock signal BOUT of the backward delay array 30 by a delay time ‘d2’ to output an internal clock signal ICLK. The internal clock signal ICLK has the same phase as the external clock signal XCLK.
The dummy load 40 is a load additionally provided so that the forward delay array 10 and the mirror control circuit 20 have a symmetric structure to the backward delay array 30 and the dummy load 40.
Referring to FIG. 3, an operational timing diagram of FIG. 1 is shown. Upon receiving an external clock signal XCLK externally applied, the input buffer IBUF generates a reference clock signal PCLK. The reference clock signal PCLK is delayed by a delay time ‘d1’ through the input buffer IBUF.
Subsequently, the delay compensation circuit DCC delays the reference clock signal PCLK by a delay time ‘d1+d2+d3’, which is the sum of the delay time ‘d1’ of the input buffer IBUF, the delay time ‘d2’ of the output buffer INTBUF, and the delay time ‘d3’ of the mirror control circuit 20.
The delayed clock signal DOUT from the delay compensation circuit DCC is fed into the forward delay array 10. The forward delay array 10 delays the delayed clock signal DOUT with the delay units FD1 to FDn in sequence. The delay time of the forward delay array 10 is ‘TCC−(d1+d2+d3)’, where TCC is the cycle of the external clock signal PCLK.
The mirror control circuit 20 compares the reference clock signal PCLK with a plurality of delayed clock signals FOUTi (i=1−n) and detects a delayed clock signal FOUTi having the same phase as the reference clock signal PCLK. Namely, the mirror control circuit 20 detects a clock signal delayed by one cycle with respect to the reference clock signal PCLK from the input buffer IBUF, i.e., a clock signal FOUTi having a phase difference of one cycle with the reference signal.
The delayed clock signal FOUTi thus detected is output as an internal clock signal ICLK through the backward delay array 30 and the output buffer INTBUF.
The total time required for acquiring synchronization of the internal clock signal ICLK with the external clock signal XCLK is given by the following equation:T=d1+(d1+d2+d3)+(TCC−(d1+d2+d3))+d3+(TCC−(d1+d2+d3))+d2=2TCC
In the above equation, ‘d1’ is the delay time of the input buffer IBUF; ‘d1+d2+d3’ is the delay time of the delay compensation circuit DCC; ‘TCC−(d1+d2+d3)’ is the delay time of the forward and backward delay arrays 10 and 30 at the time when the reference clock signal PCLK applied to the mirror control circuit 20 is synchronized with the clock signal passing through the forward delay array 10; and ‘d2’ is the delay time of the output buffer INTBUF.
As can be seen from the above equation, the internal clock signal ICLK is synchronized with the external clock signal XCLK after two cycles. Namely, the internal clock signal ICLK is in synchronization with the (n+2)-th external clock signal XCLK with respect to the n-th external clock signal, as illustrated in FIG. 3. Consequently, the internal clock signal ICLK synchronized with the external clock signal XCLK is generated two cycles after an input of the external clock signal XCLK.
U.S. Pat. No. 6,643,219 discloses an example of the kind of SMD circuit as shown in FIGS. 1–3 above. In such a conventional SMD circuit, a desired delay cannot be acquired because of a large loading capacitance of the delay unit when a reference clock signal is applied to the mirror control circuit.
FIG. 4 shows a reference clock signal PCLK1 fed into the phase detector of a first unit in the conventional reference clock signal, and a reference clock signal PCLK2 fed into the phase detector of a last unit.
As shown in FIG. 4, there is a difference between the reference clock signal PCLK1 fed into the phase detector of the first unit and the reference clock signal fed into the phase detector of the last unit. The loading capacitance on the clock line causes a distortion or a delay of the reference clock signal by a delay time of ‘td’.
This means the difference of the reference clock signals of the synchronous mirror control circuit leads to errors when the internal clock signal is synchronized with the reference clock signal. Namely, the reference clock signal is fed into the respective phase detectors of the mirror control circuit to cause a delay time according to the input load, making it difficult to acquire accurate synchronization.